Sub-100 nm NMOS Halo工艺优化分析  

Analysis and Optimization of Sub-100 nm NMOS with Halo

作　　者：汪洋[1] 王兵冰[1] 黄如[2] 张兴[2] 

机构地区：[1]北京大学深圳研究生院,广东深圳518055 [2]北京大学微电子学系,北京100871

出　　处：《固体电子学研究与进展》2006年第4期445-449,共5页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(90207004)

摘　　要：短沟道效应是MOS器件特征尺寸进入Sub-100nm后必须面对的关键挑战之一。Halo结构能够有效地抑制短沟道效应,合理的Halo区掺杂分布会极大地改善小尺寸器件性能。文中采用器件和工艺模拟工具ISE-TCAD研究形成Halo结构的工艺参数对器件性能的影响,并进行优化。分析表明,Halo注入角度、能量和剂量的增大会提高器件的阈值电压和开关比,降低泄漏电流和阈值漂移,有效抑制SCE、DIBL效应,但同时也会部分地降低驱动能力,即Halo注入参数对器件性能的影响不是简单的线性关系,需要根据具体条件寻求优化值。The Short-channel effect （SCE） is one of the key challenges we have to deal with when the feature size of the MOS devices is scaling down into the sub-100 nm regime. The Halo structure device can restrain the SCE effectively, and improve the device performance greatly with good doping distribution in the Halo region. In this paper, influence of Halo process parameter on device performance is researched and optimized with ISE-TCAD tools. It is found that higher tilt angle, energy and dosage gives increased threshold voltage and radio of Ion to Ioff,and also reduced leakage current and threshold shift, but reduced drive current which means that it is not a simple linear relation between implantation parameters and device performance and an optimized result is needed to get according to the requirements.

关 键 词：HALO 短沟道效应 离子注入 掺杂分布 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN305.3