2.5Gbps/ch两通道并行时钟数据恢复电路  

2.5Gbps/ch 2-Channel Parallel Clock and Data Recovery Circuit

作　　者：刘永旺[1] 王志功[1] 李伟[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《Journal of Semiconductors》2007年第3期460-464,共5页半导体学报（英文版）

摘　　要：采用TSMC公司标准的0.18μm CMOS工艺,结合锁相环和延迟锁相环技术,设计并制作了一个全集成的2.5Gbps/ch并行时钟数据恢复电路.与传统并行数据恢复电路相比,该电路不需要本地参考时钟,并且恢复出的并行数据是位同步的.输入2路并行的231-1PRBS数据,恢复出的2.5GHz时钟的均方抖动值为2.6ps,恢复出的两路2.5Gb/s数据的均方抖动值分别为3.3ps和3.4ps.A monolithic 2.5Gbps/ch 2-channel parallel clock and data recovery circuit is designed and fabricated in TSMC＇s standard 0.18μm CMOS process. PLL and DLL techniques are applied to implement the IC. Compared with conventional circuits,the recovered parallel data is bit-synchronous,and the reference clock is avoided. The rms jitter of the recovered clock is 2.6ps for 2 parallel PRBS input data （231 - 1）. The rms jitters of the two recovered data are 3. 3 and 3. 4ps,respectively.

关 键 词：并行时钟数据恢复 锁相环 延迟锁相环 位同步 

分 类 号：TN79[电子电信—电路与系统]