一种RISC微处理器的快速乘除法运算设计与实现  

Design and Implementation of Fast Computation for Multiplication and Division Embedded in RISC Processor

作　　者：王江[1] 黄秀荪[1] 陈刚[2] 杨旭光[2] 仇玉林[1] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]北京华控技术有限责任公司,北京100085

出　　处：《电子器件》2007年第1期162-166,共5页Chinese Journal of Electron Devices

摘　　要：定点尾数乘除法器是相应32位浮点运算的核心部件,针对工控应用,本文采用半定制方法完成了设计并且采用TSMC0.18微米工艺实现.乘法器采用基4Booth编码,通过对符号位、隐含位的处理减少了部分积的生成,并在Wallace树求和过程中,引入4:2压缩器,加快了求和速度.除法器采用改进的SRT算法,引入商位猜测、部分余并行计算、商位修正值选择电路.乘除法器均采用了进位保留加法器提高运算速度.后端物理实现表明,乘除法器的频率分别可到227MHz,305MHz,整体设计具有简洁、快速、计算准确的特征.Multiplier and divider embedded in RISC CPU were designed and implemented in TSMC 0. 18 micrometer process. The carry saved adder and carry look ahead adder were used in the circuits. By carefully optimization, the quantity of partial products generation could be lowered, and the efficiency of the Wallace summing enhanced. The multiplier could be used in pipelined mode to improve the efficiency of CPU, and the divider, by means of modified SRT algorithm, the accuracy of division could be acquired. By adopting the quotient guess, parallel remainder computing, and modified bit selecting circuits, the fast speed is acquired. The physical implementation result shows that the speed of Multiplier and Divider could be 227 MHz, 305 MHz, respectively. The circuits are accurate and effident for the industrial automation applications.

关 键 词：保留进位加法器 布斯编码 乘法器 除法器 集成电路设计 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]