基于全状态伪随机序列的BIST设计  

The Research and Design BIST Based All Status Pseudo-Random Sequence Generators

作　　者：段颖妮[1] 吕虹[1] 张海峰[2] 

机构地区：[1]安徽工程科技学院电气系,安徽芜湖241000 [2]暨南大学光电工程研究所,广州510632

出　　处：《电子器件》2006年第4期1263-1266,共4页Chinese Journal of Electron Devices

基　　金：安徽省自然科学基金资助项目(050420203)

摘　　要：全状态伪随机序列发生器(ASPRG)是在FSR的基础上,通过修改其反馈函数而得到,其最大的优点就是利用了移位寄存器的全部状态,序列最大长度为2n。本文首先推导得到4位和8位ASPRG的反馈网络函数,在此基础上应用ASPRG进行内建自测试(Build In Self Test)设计并优化电路结构,ASPRG既作为测试信号发生器,而它的另一种工作模式则作为特征分析使用。这样不仅简化了BIST设计,同时降低了功耗,具有较高的现实意义。The All-Status Pseudo-Random sequence Generator （ASPRG） is based on the FSR, obtained that through modifying its feedback transfer function, its biggest merit is that the shift register states are all used the greatest length is 2^n. The paper obtained 4-bit and 8-bit feedback function of ASPRG by deduction, then carried on design the BIST using ASPRG and optimized electric circuit structure, the ASPRG is used as the test sequence generator, but its another kind of working pattern was used to characteristic analysis. Not only simplified the BIST design, simultaneously reduced the power loss, and has the higher practical significance.

关 键 词：全状态 伪随机序列 内建自测试 移位寄存器 特征分析 

分 类 号：TN407[电子电信—微电子学与固体电子学]