0.6μm CMOS分布式放大器设计  

Design of 0.6 μm CMOS Distributed Amplifier

作　　者：陈勖[1] 王志功[1] 李伟[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《固体电子学研究与进展》2007年第1期58-62,共5页Research & Progress of SSE

摘　　要：采用了国内0．6μm标准CMOS工艺设计实现了一种单片集成的分布式放大器。放大器采用四级级联结构，单元电路采用管联（cascode）结构以提高隔离度。在输人输出端50Ω匹配情况下，测试得到的频带宽度为0．1～4.0GHz，增益为5.0±1.0dB，输入输出的回波损耗分别小于-10dB和-7dB。在5V供电下功耗约为110mW。This paper presents the design of a fully-integrated four-stage distributed amplifier in standard 0.6 μm CMOS technology. The individual cell of the four cascaded stages is based on a cascode configuration to increase the isolation. On-wafer measurements have shown that this distributed amplifier achieved a gain 5.0± 1.0 dB from 0. 1 to 4.0 GHz when the input and output terminals are matched to 50 Ω, with the S11〈-10 dB and S22〈-7 dB. The power consumption is about 110mW under a 5 V supply.

关 键 词：分布式放大器 电感 互补金属氯化物半导体 管联结构 

分 类 号：TN72[电子电信—电路与系统]