集成模乘求逆双重运算的抗攻击RSA协处理器  

Attack-resisted RSA Coprocessor Integrating Multiplication and Inverse

作　　者：韩军[1] 曾晓洋[1] 陆荣华[1] 赵佳[1] 汤庭鳌[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《小型微型计算机系统》2007年第4期753-758,共6页Journal of Chinese Computer Systems

基　　金：国家自然科学基金(90407002;60576024)资助;上海市科委AM基金(0502)资助.

摘　　要：提出了一种集成模乘求逆双重运算的抗攻击RSA协处理器设计.在设计中引入了指数重编码和双位扫描的方法以提高模幂运算的速度,并采用数据屏蔽和随机重编码的方案来防御功耗分析攻击.基于字串行架构实现了模乘和求逆运算,并提出了相应的可伸缩蒙哥马利模乘算法,使基本运算具有数据通路小、可伸缩性强的特点.在VLSI设计上实现了模乘和求逆运算的硬件复用,大幅度地降低了成本.FPGA验证表明协处理器能够正确地完成所有预定的功能.TSMC0.25um工艺综合结果显示,协处理器的工作频率可达170MHZ,总的规模(包括核心电路与存储单元)约为26K等效门.因此本文RSA协处理器体现了多功能、可伸缩、抗攻击和低成本的综合优势.An attack-resisted RSA coprocessor integrating multiplication and inverse is presented in this paper. The exponent recoding and dual-bit scanning techniques can speed up computing are added into exponentiation algorithm. The data masking and randomly recoding methods are also adopted to resist DPA attack. The digit-serial architecture is used in Montgomery multiplication and inverse, so the scalable Montgomery multiplication algorithm corresponding to small data path is presented by us. In VLSI design, the hardware reuse technique is employed to save area costs. The verification of design＇s functions is fulfilled by FPGA based platform. The design is also synthesized with TSMC 0. 25 technology and it costs 26K gates at 170MHZ. So the merits of our design are multiple functions, scalable, attack-resisted and low cost.

关 键 词：RSA协处理器 指数重编码 模乘 求逆 可伸缩 低成本 功耗分析攻击 

分 类 号：TN492[电子电信—微电子学与固体电子学] TP309[自动化与计算机技术—计算机系统结构]