适用于0.8μmCMOS VLSI的双层金属布线技术研究  

Investigation of Doublelevel Metallization Technology for 0.8μm CMOS VLSI Application

作　　者：徐秋霞[1] 海潮和[1] 陈焕章[1] 赵玉印[1] 李建勋 

机构地区：[1]中国科学院微电子中心研究部,北京100029

出　　处：《Journal of Semiconductors》1997年第3期218-222,共5页半导体学报（英文版）

摘　　要：多层金属有线互连技术是VLSI工艺中最重要和关键的技术之一．本文系统地研究了用效0．8μmCMOSVLSI的双层金属布线工艺技术，特别是对双层金属布线层间介质的平坦化、接触孔和通孔的低阻欧姆接触及可靠的金属互连等关键工艺进行了分析讨论．这套技术已成功地应用放“0．8μm双层金属布线CMOS计算机主板时钟产生器专用集成电路”的研制，并获得较好芯片成品率．Multilevel metallization is one of the most important and key technologies in VLSI. This paper has investigated double level metallization technology used for 0.8μm CMOS VLSI systematically. In particular, key technologies of dielectric planarization techniques for double level metallization, and low contact resistance of contact window and via, as well as reliable metal interconnection system etc., have been analyzed and discussed. This set of technology has been applied successfully to developing 0.8μm double level metallization CMOS clock generator ASIC of PC main board, and good yield of chip is obtained.

关 键 词：多层布线技术 VLSI CMOS 

分 类 号：TN470.597[电子电信—微电子学与固体电子学]