基于March C-算法的SRAM BIST电路的设计  

SRAM BIST Circuit Design Based on the March C-Algorithm

作　　者：须自明[1] 苏彦鹏[1] 于宗光[1] 

机构地区：[1]江南大学信息工程学院,江苏无锡214000

出　　处：《半导体技术》2007年第3期245-247,共3页Semiconductor Technology

基　　金：电子元器件可靠性物理及其应用技术国防科技重点实验室资助项目(51433020105DZ6802)

摘　　要：针对某SOC中嵌入的8K SRAM模块,讨论了基于March C-算法的BIST电路的设计。根据SRAM的故障模型和测试算法的故障覆盖率,研究了测试算法的选择、数据背景的产生,并完成了基于March C-算法的BIST电路的设计。实验证明,该算法的BIST实现能大幅提高故障覆盖率。According to the 8K SRAM module of SOC, a BIST （built in self test） circuit design based on the March C-algorithm was discussed. The choose of the test algorithm, the generation of the database were studied, and the main part of the BIST design was worked out, based on the fault models of SRAM and the fault coverage of the test algorithm. The conclusions prove that the approach can improve the fault coverage obviously.

关 键 词：静态存储器 MARCH C-算法 内建自测试 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]