一种有效的golomb解码器设计与硬件实现  

Architecture Design and Hardware Implementation for Golomb Decoder

作　　者：王小强[1] 秦水介[1] 

机构地区：[1]贵州大学光电子技术及应用贵州省重点实验室

出　　处：《安阳师范学院学报》2007年第2期48-51,共4页Journal of Anyang Normal University

基　　金：国家自然科学基金项目(项目编号:50375031);2003年度教育部优秀青年教师资助计划项目;春晖计划项目;贵州省科学基金(No.3014;No.3005)

摘　　要：Golomb编码压缩算法已被广泛地应用于视频图像处理、测试数据压缩等众多领域。本文设计了一种有效的适合硬件实现的Golomb解码器,并且完成了解码器电路的硬件实现。本设计采用有限状态机(FSM)与计数器相结合的解码结构,并且对有限状态机的实现进行了优化,减少了有限状态机的状态数。电路综合实验结果表明,此解码器的电路门数大约为120门,关键路径延时为0.7ns。该设计可扩展性强、硬件开销少,可在较高的工作频率下工作,并且可以作为独立的IP核使用。The Golomb codes have been widely used in many fields such as video and image process, test - data compression. In this paper, an efficient Golomb decoder architecture has been designed, which is suitable for implementation. We also accomplish the hardware implementation of the decoder circuit. The architecture of the de- coder is composed of finitestate machine （FSM） module and counter module. We reduce the state number of the finite - state machine by optimizing it. The synthesis result shows that the areas of the decoder are about 120 gates and the critical path delays are 0.7ns. This design is scalable and can meet the requirement of high working frequency. In addition, the hardware overhead of the decoder is very small and the design can become independent IP core.

关 键 词：Golomb编码 解码器 变长编码 有限状态机 测试数据压缩 

分 类 号：TN402[电子电信—微电子学与固体电子学]