16位中央处理器设计与现场可编程门阵列实现  

16-bit CPU Design and FPGA Implementation

作　　者：白广治[1] 陈泉根[1] 

机构地区：[1]中国工程物理研究院电子工程研究所,四川绵阳621900

出　　处：《信息与电子工程》2007年第3期206-210,共5页information and electronic engineering

摘　　要：为了自主开发中央处理器(Central Processing Unit,CPU),对16位CPU进行了研究,提出了以执行周期尽量最少的译码执行方式,采用Top-Down的方法进行设计,用硬件描述语言Verilog进行代码编写,并对编写的CPU代码进行仿真验证和现场可编程门阵列(Field Programmable Gate Array,FPGA)验证。结果表明,该CPU运行效率较INTEL等通用CPU有较大提高。该自主CPU可以作为IP核进行FPGA应用,也可进行SoC设计应用。A 16-bit CPU is studied in this paper. With the decoding method which has almost the least executing cycles, it is designed by Top-Down method. It is programmed in hardware description language--Verilog. Simulation verification and FPGA verification are performed to the code. The verification results indicate that the 16-bit CPU work higher efficiently than general CPU such as INTEL. It can be used in FPGA as IP core. Furthermore, it can be used in SoC design as well.

关 键 词：中央处理器 现场可编程门阵列 IP核 VERILOG 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]