击穿18V的高压LDD PMOS器件的研制  

Fabrication of High Voltage LDD PMOS Devices with Breakdown Voltage of 18V

作　　者：王晓慧[1] 杜寰[1] 韩郑生[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2007年第7期72-75,共4页Microelectronics & Computer

基　　金：国家重点基础研究发展计划项目(2003CB314705)

摘　　要：从Synopsys TCAD的软件模拟出发,基于0.8μm标准CMOS工艺,通过重新设计高压N阱,以及优化器件LDD区域注入剂量,成功研制了栅长0.8μm击穿电压达到18V的LDD结构的高压PMOS器件,并实现了低高压工艺的兼容。研制的宽长比为18/0.8的PMOS器件截止电流在500pA以下,阈值电压为-1.5V,-10V栅压下饱和电流为-5.6mA,击穿电压为-19V。器件主要优点是关态漏电小,且器件尺寸不增加,不影响集成度,满足微显示像素驱动电路对高压器件的尺寸要求,另外与其他高压器件相比更容易实现,节约了成本。In this paper, high voltage （HV） LDD PMOS devices with breakdown voltage of 18V have been fabricated based on 0.8μm standard CMOS process which belongs to IMECAS （Institute of Microelectronics of Chinese Academy of Sciences）. To raise devices breakdown voltage, a lower impurity concentration and deeper HVN-well was designed and the LDD region implantation dose was decreased. This HV process is completely compatible with standard CMOS process. The device with W/L of 18：0.8 has a threshold voltage of about -1.5V, a leakage current of 500pA, a breakdown voltage of -19V, and a driving current of -5.6mA when the gate voltage is -10V. The HV device has the advantages of small off-state leakage current and un-increased size. It＇s suitable to be used in micro-display pixel driving circuits.

关 键 词：高压PMOS器件 轻掺杂漏 击穿电压 器件模拟 

分 类 号：TN386.1[电子电信—物理电子学] TN453