基于扫描链结构重组的低功耗BIST方案  

Low-Power BIST Methodology Based on Scan-Chain Reorder

作　　者：李俊[1] 成立[1] 徐志春[1] 韩庆福[1] 张荣标[1] 张慧[1] 

机构地区：[1]江苏大学电气与信息工程学院,江苏镇江212013

出　　处：《半导体技术》2007年第9期757-760,764,共5页Semiconductor Technology

基　　金：国家863计划资助项目(2006AA102258)

摘　　要：设计了一种改进扫描链结构的内建自测试(BIST)方案。该方案将设计测试序列发生器(TPG)中合适的n状态平滑器与扫描链的重新排序结合起来,从而达到低功耗测试且不致丢失故障覆盖率的目的。通过对15位随机序列信号的测试,发现此TPG中的n状态平滑器在降低功耗的同时还减小了故障覆盖率,遂又设计了重组扫描链的结构来解决这一问题。实验结果表明,该设计方案对于降低平均测试功耗和提高故障覆盖率都具有显著的效果。A kind of low-power testing methodology for the scan-based built-in self-test （BIST） was proposed, It combines a low-power test pattern generator （TPG） which contains an n-state smoother and scan-chain reordering to achieve low-power testing without losing fault coverage, Through the experiment of 15 random sequences test, the fault coverage might be adversely affected by the smoother, hence, a clusterbased scan-chain reordering was employed to remedy this problem, Experimental results show that the proposed method has the remarkable effect on the reduction of average test power and the improvement of fault coverage.

关 键 词：内建自测试 测试序列发生器 n状态平滑器 低功耗设计 

分 类 号：TN407[电子电信—微电子学与固体电子学]