基于优化时间重叠技术的并行流水线A/D转换器  

Design of Parallel Pipelined A/D Converter Based on Optimized Time Interleaving

作　　者：张思栋[1] 黄鲁[1] 林贝元[1] 

机构地区：[1]中国科学技术大学电子科学与技术系,合肥230027

出　　处：《微电子学》2007年第5期712-716,共5页Microelectronics

摘　　要：提出了一种基于优化时间重叠技术的10位300 MHz采样率4路并行流水线A/D转换器的设计方法,该方法降低了对运算放大器的要求。通过理论计算和实例设计,证明了此低功耗设计方法的显著效果。设计了一个用于前端的运算放大器,在CSM 0.35μm CMOS工艺、3.3 V电源电压下,该运放的增益为106 dB,单位增益带宽为402 MHz,建立时间为8.8 ns。采用优化时间重叠技术后,可满足4路并行300 MHz采样率的要求,功耗仅为8.57 mW,可大大降低整个并行流水线A/D转换器的功耗。A 10-bit 300-MHz 4-channel parallel pipeline A/D converter was designed. The proposed design relaxed the requirement for op-amps by optimizing the traditional time-interleaving technique. Both theoretic analysis and simulation demonstrated that the method had a significant improvement on low power dissipation design. A frontend op-amp was also designed. HSPICE simulation based on CSM＇s 0. 35 μm CMOS technology show that, with 3.3 V power supply, the op-amp has an open-loop gain of 106 dB, a unity gain bandwidth of 402 MHz and a settling time of 8.8 ns, which, by optimizing the time interleaving technique, can meet the requirement of 4-channel 300- MHz sampling rate. The op-amp consumes only 8. 57 mW of power, significantly reducing the total power of the parallel pipelined A/D converter.

关 键 词：并行流水线A/D转换器 时间重叠 低功耗运算放大器 采样保持电路 

分 类 号：TN402[电子电信—微电子学与固体电子学]