一种有效降低测试时间的SOC扫描测试设计方法  

Effective Design Method to Reduce SCAN Test Application Time of SOC's

作　　者：石亦欣[1] 李蔚[1] 俞军[1] 程君侠[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《微电子学》2007年第5期756-760,共5页Microelectronics

摘　　要：随着集成电路规模的迅速增大,巨大的测试向量带来的测试成本压力已成为芯片产品成本考虑中一个不可忽略、甚至非常关键的要素。针对目前大规模SOC芯片测试成本高的问题,提出了一种通过测试扫描链复用来减少测试时间的方法。试验数据表明,该方法在降低测试时间的同时,保持了较高的测试覆盖率,是一种较有价值的降低SOC芯片测试成本的方法。The large size of the scan test data volume has become a significant factor in the overall production costs of IC＇s, due to the long test application time. In order to reduce the cost for large-scale SOC test, a DFT method to reuse the scan chain was proposed to reduce the scan shift time. Tests were conducted using the new method, and results were compared with those using the traditional method. It has been shown that the proposed method can reduce the test application time of SOC＇s, while maintaining a relatively high test coverage rate.

关 键 词：SOC 可测试性设计 扫描测试 扫描测试向量压缩技术 自动测试向量产生 

分 类 号：TN407[电子电信—微电子学与固体电子学]