基于FPGA的高速异步FIFO存储器设计  

Design of high-speed asynchronous FIFO memory based on VHDL

作　　者：杨军[1] 孔兵[1] 宋克俭[1] 尹航[1] 

机构地区：[1]云南大学信息学院,云南昆明650091

出　　处：《云南大学学报（自然科学版）》2007年第6期560-565,569,共7页Journal of Yunnan University(Natural Sciences Edition)

基　　金：云南省教育厅科学研究基金项目(6Y0046D)

摘　　要：介绍异步FIFO存储器应用及其结构,详细分析了异步FIFO的标志逻辑设计及亚稳态的消除,提出了一种基于FPGA芯片利用格雷码对地址编码解决异步读、写时钟问题的思路及方法,并给出了VHDL程序.该方法具有高速、可移植性强、工作效率高的特点,在数字系统设计中具有一定的意义和应用价值.It is presented the asynchronous FIFO memory structure and its applications. It was analysised the asynchronous FIFO memory flags logic design and eliminate metastability. It is proposed an approach based on FPGA chips by using Grey code to address coding solution asynchronous reading and writing of the ideas and methods clock,and show a code of VHDL. The method has portability strong,efficient features which can be widely used digital system design related.

关 键 词：异步FIFO 标志逻辑 格雷码 亚稳态 FPGA VHDL 

分 类 号：TP333.5[自动化与计算机技术—计算机系统结构]