适用于半速率CDR改进型VCO的设计与实现  

Design and Implementation of Improved VCO for Half-Rate CDR Circuit

作　　者：唐世民[1] 何小威[2] 陈吉华[2] 陈怒兴[2] 

机构地区：[1]西南电子电信研究所,成都610041 [2]国防科技大学计算机学院微电子与微处理器研究所,长沙410073

出　　处：《半导体技术》2008年第1期35-38,共4页Semiconductor Technology

摘　　要：在0.13μm数字CMOS工艺下设计实现了一种改进型的差分振荡器电路，该电路采用四级环形结构，其中心工作频率为1.25GHz，版图面积为50μm×50μm，工作范围1．1-1.4GHz，VCO的增益约为300MHz／V，在1.2V电源电压下、工作频率为1.25GHz时的平均功耗约为10mW。版图后模拟结果表明，该VCO输出的四相时钟信号间隔均匀，占空比接近50％，可适用于基于PLL的2．5Gbps的半速率时钟数据恢复电路。An improved full differential four stage ring VCO was developed, with 50μm - 50 μm chip area. The VCO is realized in 0.13 μm digital CMOS process, and its center frequency is 1.25 GHz. The operating frequency range of the VCO is 1.1 to 1.4 GHz with the gain of 300 MHz/V. The average power consumption is about 10 mW at a supplied voltage of 1.2 V and an operating frequency of 1.25 GHz. The post simulation result shows that the output quadrature phase clocks are evenly spaced with almost 50% duty cycle, and can be used in a half-rate clock and data recovery circuit based on PLL.

关 键 词：压控振荡器 时钟数据恢复 半速率 

分 类 号：TN752[电子电信—电路与系统]