高性能绝缘层上应变硅动态阈值MOSFET的设计优化  

Design Optimization of High Performance Strained SOI Dynamic Threshold MOSFET's

作　　者：李德斌[1] 梁仁荣[1] 刘道广[1] 许军[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《微电子学》2008年第1期72-75,80,共5页Microelectronics

基　　金：国家自然科学基金资助项目(60476017,60636010)

摘　　要：采用二维数值模拟的方法,研究了纳米尺度栅长的绝缘层上应变硅(SSOI)动态阈值(DT) MOSFET的特性,全面分析了台阶型沟道掺杂分布和沟道长度对器件开态和关态特性的影响。结果表明,通过调整轻掺杂的表面沟道和重掺杂的体杂质分布,DT SSOI器件能在较低的电源电压下实现比非DT器件更优的性能,同时不会造成明显的器件关态漏电。从实验结果可以预测,相对于非DT器件而言,DT器件在性能上的这种优势能够保持到32 nm栅长的技术节点。2-D device simulations were performed to investigate strained SOI （SSOI） dynamic threshold （DT） MOSFET＇s in nano-scaled gate length regime. The influence of the stepped channel doping and channel length on the on- and off-state characteristics was Comprehensively analyzed. It has been shown that DT SSOI can achieve higher performance than the non-DT SSOI even under relatively lower power supply, without significant degradation of the off-state leakage, by adjusting the doping profile of the lightly doped surface channel and the heavily doped body. From this work, it can he predicted that the advantages of DT devices over non-DT devices are able to he hold on to the 32-nm gate length technology node.

关 键 词：绝缘层上应变硅 动态阈值 MOSFET 台阶掺杂 

分 类 号：TN386[电子电信—物理电子学]