一类基于无竞争编码FSM的数字系统设计方案  

Digital System design using the coding scheme with Non-competition hazard

作　　者：楼玲娣[1] 何剑春[1] 俞立[1] 

机构地区：[1]浙江工业大学信息工程学院,浙江杭州310032

出　　处：《浙江工业大学学报》2008年第1期57-61,共5页Journal of Zhejiang University of Technology

基　　金：浙江省教育厅资助科研项目(20051399)

摘　　要：数字系统设计中,时序电路模块的状态分配过程是一个必须重视的环节.针对"数字系统设计和实践"课程中常见的竞争冒险问题,以四位数字频率计为例,采用VHDL语言,利用Quartus II平台,设计了控制器CONSIGNAL、4个十进制计数模块CNT10)、4个锁存模块LOCK和4个显示译码模块DECODER等功能模块,对基于二进制状态编码的控制器和基于无竞争状态编码的控制器进行仿真比较,提出一类基于无竞争编码有限状态机(FSM)的设计方案,以避免竞争冒险现象.仿真结果表明该方案的正确性和有效性.During the design flow in digital systems, the state allocation problem in the timing circuit module is an important issue. As an example, a 4-bit-cymometer is discussed here. VHDL is used to describe the blocks, such as controller CONSIGNAL, four counter modules CNT10, four latch modules and four display decoders in the system. Based on binary encoding and the controller with non- competition encoding, in order to eliminate the competition and adventure, a FSM approach is presented to realize the 4-bit-cymometer based on Quartus Ⅱ 6.0 with non-competition. Both the comparisons and the simulation results show that this method is correct and effective.

关 键 词：状态分配 竞争冒险 有限状态机 频率计 

分 类 号：TN762[电子电信—电路与系统]