基于双DSP的嵌入式导航计算机分布式系统设计  

Design of distributed system for embedded navigation computer system based on dual DSPs

作　　者：张国龙[1] 徐晓苏[1] 扶文树[2] 

机构地区：[1]东南大学仪器科学与工程学院,南京210096 [2]南京北方信息产业集团有限公司,南京211153

出　　处：《中国惯性技术学报》2008年第1期64-67,共4页Journal of Chinese Inertial Technology

基　　金：国防科技重点预研项目(51309020503);国家自然科学基金项目(50575042);教育部博士点专项科研基金项目(20050286026)

摘　　要：为了满足 SINS/GPS 组合导航系统的小型化、低功耗、低成本等条件,以及越来越高的精度要求,设计了基于双 DSP 和 FPGA 构成的嵌入式导航计算机分布式系统。该系统由 TI 公司 TMS320C6701 型和 TMS320VC33型 DSP 芯片作为核心处理器,主要完成导航计算和在线滤波校正算法;由 FPGA 实现输入输出等外围接口,完成对 IMU 信号的采集控制和缓存、多串行口的扩展等功能。DSP 通过外部存储器接口(EMIF)实现与 FPGA 的通信,可以一次以 DMA(Direct Memory Access)的方式从 FPGA 中 FIFO 快速读取 IMU 以及 GPS 的数据,使得 DSP能专注于导航计算;另外,导航计算和在线滤波校正任务在不同的 DSP 中完成,能有效提高系统的精度,更好地满足系统实时性要求。To meet the requirements of SINS/GPS integrated navigation system, a distributed embedded navigation computer system based on dual DSPs and FPGA was designed. In the system, the navigation algorithm and the error-correcting algorithm was mainly executed in the core of DSP chips TMS320C6701 and TMS320VC33 which are produced by TI. And the I/O interface function was realized by FPGA which performed the IMU signal acquisition, buffering data and expanding multi-UART. The communication between DSP and FPGA was achieved by DSP＇s External Memory Interface（EMIF）. In this way, the data of IMU and GPS could be read fleetly from the FIFO of FPGA by Direct Memory Access（DMA）, so that DSPs could be devoted in navigation algorithm. In addition, the two algorithms were executed in respective DSP. So the distributed system scheme can improve the precision of the system effectively, and enhance the real-time performance of the system.

关 键 词：组合导航 嵌入式导航计算机 DSP FPGA 

分 类 号：U666.1[交通运输工程—船舶及航道工程]