高压MOS晶体管双峰衬底电流分析及优化  

Analysis and Optimization for the Double-Hump Substrate Current of High-Voltage MOS Transistors

作　　者：王俊[1] 董业民 邹欣 邵丽 李文军 杨华岳 

机构地区：[1]中国科学院上海微系统与信息技术研究所 [2]上海宏力半导体制造有限公司,上海201203

出　　处：《半导体技术》2008年第4期316-319,共4页Semiconductor Technology

摘　　要：利用0.15μm标准CMOS工艺制造出了工作电压为30V的双扩散漏端MOS晶体管。观察到DDDMOS的衬底电流-栅压曲线有两个峰。实验表明,DDDMOS衬底电流的第二个峰对器件的可靠性有一定的影响。利用TCAD模拟解释了DDDMOS第二个衬底电流峰的形成机制,并通过求解泊松方程和电流连续性方程分析了器件的物理和几何参数与第二个衬底电流峰之间的关系。根据分析的结果优化了制造工艺,降低了DDDMOS的衬底电流,提高了器件的可靠性。A 30 V double diffused drain MOS （DDDMOS） was fabricated with standard 0.15 μm CMOS process. The substrate current was investigated and the two humps of Ib- Vg curves were observed. Experiments show that the second hump of substrate current would have impact on the reliability of device. The origin was demonstrated by TCAD simulation. The correlation between the electric field and the device parameters was studied through poisson equation and current continuity equation. Based on the analysis, an improved process is obtained, achieving much lower substrate current and better reliability performance.

关 键 词：高压器件 衬底电流 优化工艺 

分 类 号：TN433[电子电信—微电子学与固体电子学]