一个基于扫描方法的DFT设计与实现  

A Scan Based DFT Design and Implementation

作　　者：张炜杰[1] 陈亦灏[1] 沈怿皓[1] 赖宗声[1] 段春丽 

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200062 [2]上海士康射频技术有限公司,上海200437

出　　处：《微电子学与计算机》2008年第5期169-172,共4页Microelectronics & Computer

基　　金：上海市科委项目(06SA14);上海市经委信息办基金项目(04-联专-001)

摘　　要：DFT技术已经成为集成电路设计的一个重要组成部分.详细介绍了基于扫描测试的DFT原理和实现步骤,并对一个32位FIFO存储器电路实例进行扫描设计.根据扫描链的特点和电路多时钟域问题,采用了三种设计方案,整个流程包括了行为级Verilog代码的修改、扫描设计综合以及自动测试模板产生(ATPG).对不同的设计方案给出了相应的故障覆盖率,并对生成的模板进行压缩优化,减少了测试仿真时间.最后分析了导致故障覆盖率不同的一些因素和设计中的综合考虑.DFT technology has become an important part in IC design. The theory and method of scan-hased test is introduced in detail and an example of 32-bit FIFO memory using DFT technology is presented. According to the characteristic of scan chains and muliti-clock in the circuit, three strategies have been used in the design from code modification, scan synthesis to the final ATPG. The result of fault coverage is presented. By compression, the patterns are optimized and the simulation time is reduced. Finally some factors and considerations have been analyzed leading to the differences of the fault coverage.

关 键 词：可测性设计 扫描测试 扫描链 故障覆盖率 

分 类 号：TN4[电子电信—微电子学与固体电子学]