薄膜全耗尽应变Si SOI MOSFET特性模拟与优化分析(英文)  

Simulation and Optimization of High Performance FD SOI MOSFET with Thin Body Strained-Si Channel

作　　者：刘静[1] 高勇[1] 王彩琳[1] 黄媛媛[1] 

机构地区：[1]西安理工大学电子工程系,西安710048

出　　处：《电子器件》2008年第3期859-863,共5页Chinese Journal of Electron Devices

基　　金：国家自然科学基金资助(50477012);高等学校博士学科点专向科研基金资助项目(20050700006)

摘　　要：研究了应变Si沟道引入对薄膜全耗尽SOI MOSFET器件特性的影响,并分析了器件特性改进的物理机理。与传统的SOI MOSFET结构相比,器件的驱动电流和峰值跨导都有明显提高,对n-FET分别为21%和16.3%,对p-FET为14.3%和10%。应变Si沟道的引入还降低了器件的阈值电压,这有益于集成电路中供电电压的降低和电路功耗的减小。另外,本文还对新结构中的Ge含量进行了优化分析,认为当Ge含量为30%时,器件有较好的电特性,而且不会增加器件制作的工艺成本。A high performance thin body strained-Si channel FD SOI MOSFET has been studied. Based on analyzing device physical mechanism, the electrical characteristics of strained-Si SOI MOSFET are discussed. It is found that the strained-Si n-FET and p-FET both show significant drive current enhancement of 21% and 14. 3% ,and peak-Gm enhancement of 16.3% and 10%, respectively. It is also confirmed that threshold-voltage decreases with increasing of Ge content, which is of benefit to the decrease of power supply voltage and circuit power consumption. Moreover, we also discuss the influence of Ge content in SiGe layer on the devices characteristics and give the optimal Ge content for device design. The optimal percentage of Ge is 30% ,which achieves high performance for strained-Si SOI MOSFET, but it does not increase hardness for device fabrication.

关 键 词：应变硅 全耗尽 驱动电流 功耗 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN451