基于MOS管亚阈值特性的模拟译码器  

Implementation of Analog Decoder Based on Subthreshold Characteristics of MOS Transistors

作　　者：杨曙辉[1] 仇玉林[2] 

机构地区：[1]北京信息科技大学光电信息与通信工程学院,北京100101 [2]中国科学院微电子研究所,北京100029

出　　处：《微电子学》2008年第3期415-419,共5页Microelectronics

基　　金：国家自然科学基金资助项目(60501007);北京市教委科技项目(KM20051772007);北京市委组织部优秀人才项目(0042D0500705);北京市中青年骨干教师项目(07660013)

摘　　要：利用MOS管亚阈值特性,构造了输入输出均为电流信号的模拟乘法器;经过变形,设计了模拟概率计算电路。以此为基础,通过晶体管级的模拟电路设计,构造了新型的网格码模拟译码器,给出了模拟译码器的译码性能。模拟结果表明,在速度一定的条件下,与采用数字电路实现的概率译码器相比,该模拟译码器在功耗和芯片面积上至少减少了一个数量级。An analog multiplier based on the subthreshold characteristics of MOS transistors was presented, which input and output current signals. And an analog probability computation circuit was designed by changing the multiplier. Based on the circuit, a novel analog decoder of trellis code was constructed. Simulation results showed that, for the same bit rate, both the power consumption and chip area of the analog decoder were reduced at least by an order of magnitude, as compared to digital decoder.

关 键 词：亚阈值 模拟译码器 网格码 概率译码 TURBO码 

分 类 号：TN432[电子电信—微电子学与固体电子学]