110V体硅LDMOS器件研究  

Research on the 110 V Bulk-Silicon LDMOS

作　　者：罗向东[1] 孙玲[1] 陈海进[1] 刘焱华[1] 孙海燕[1] 徐炜炜[1] 陶涛[1] 程梦璋[1] 景为平[1] 

机构地区：[1]南通大学江苏省专用集成电路设计重点实验室,江苏南通226019

出　　处：《南通大学学报（自然科学版）》2008年第2期1-5,共5页Journal of Nantong University(Natural Science Edition)　

基　　金：江苏省六大人才高峰项目;南通市应用研究计划项目(K2007016);南通大学自然科学基金项目(07Z122)

摘　　要：利用SILVACO TCAD工艺仿真和器件仿真软件研究了110 V体硅LDMOS器件的几个重要参数对器件耐压特性的影响.研究结果表明,漂移区剂量存在一个最优值,过大将导致漂移区难以耗尽而使得沟道与漂移区边界发生击穿,而过小则导致漂移区迅速耗尽而在漏端表面发生击穿;衬底浓度低对提高开态击穿电压有一定效果,但低浓度衬底难以在CMOS工艺中使用;场氧与P阱和漂移区的PN结界面距离在零或者略大于零时器件耐压性有最优值;栅极板长度存在最优值,栅极板过长或过短都将使得器件的击穿电压有所降低.In this paper, the effects of breakdown voltages on the drift dose, the substrate concentration, the field oxide position from the PN junction of P-well and N-drift, and the gate field plate on field oxide have been studied in detail by SILVACO TCAD tools. By simulation, the drift dose has got an optimized value of high breakdown voltage to our designed LDMOS; lower substrate concentration causes higher breakdown voltage, but can hardly be applied to CMOS technology; when the field oxide position is close to the PN junction of P-well and N-drift, higher breakdown voltage can be achieved; when the length of the gate field plate was 1/3 to 1/2 of length of the drift region, there exists an optimized breakdown voltage.

关 键 词：高压 LDMOS 击穿电压 仿真 

分 类 号：TN710[电子电信—电路与系统] TN432