超前进位加法器研究  

Research on Carry Look-Ahead Adder

作　　者：唐金艺[1] 

机构地区：[1]海军计算技术研究所,北京100841

出　　处：《现代计算机》2008年第6期17-18,42,共3页Modern Computer

摘　　要：从硬件底层优化设计考虑,将串行加法转变为超前进位加法来提高底层的运算速度。通过设计超前进位加法将迭代关系去掉,使各变量运算彼此相对独立,避免进位传播,来降低门级层数,最终提高运算速度。Introduces the optimization design method of changing the serial adder to the carry look-ahead adder to increase the computing speed of the low level hardware. By removing the iterative relation, carry look-ahead addition makes the variables independent from each other, avoids carry spread and reduces the gate level number.

关 键 词：全加器 超前进位加法器 串行加法器 硬件 

分 类 号：TP332.21[自动化与计算机技术—计算机系统结构]