基于DVI的时钟数据恢复电路设计  

A Clock and Data Recovery Circuit Based on DVI

作　　者：肖剑[1] 陈贵灿[2] 张福甲[1] 王永顺[3] 

机构地区：[1]兰州大学物理科学与技术学院,兰州730000 [2]西安交通大学微电子研究所,西安710049 [3]兰州交通大学电子与信息工程学院,兰州730070

出　　处：《Journal of Semiconductors》2008年第7期1417-1421,共5页半导体学报（英文版）

基　　金：国家自然科学基金(批准号:60676033);西安市科技计划创新基金(批准号:GG04001)资助项目~~

摘　　要：设计了一种实现DVI(digital visual interface)数字视频信号接收器的新型时钟数据恢复电路.通过在过采样电路和数字锁相环之间增加弹性缓冲电路,在实现10bit数据恢复的同时,使采样时钟频率减小为数据频率的2.5倍,DPLL同时对10bit并行的数据进行相位检测判断,提高了判断的正确率,使数据传输的误码率得到改善.采用SMIC0.18μm CMOS工艺流片,测试结果表明,输入三路并行的1.65Gbps/ch UXGA格式像素数据和传输电缆长度2m条件下,输出系统时钟信号最大抖动峰-峰值为183ps,均方值为24ps,满足DVI规范要求.A novel clock and data recovery circuit has been designed to implement a digital visual interface （DVI） receiver. A flexible buffer was placed between the over-sampler and DPLL. Not only was 10bits data recovery implemented, but also the frequency of sampling clock was reduced to 2.5 times of the data frequency. The phase verification for 10bit parallel data by DPLL increases the accuracy rate of judgment and improves the bit error rate. The receiver has been fabricated with an SMIC 0. 18μm CMOS process. The testing results show that the maximum peak-peak and RMS jitters of the output system clock are 183ps and 24ps, respectively,under the measuring condition that the data rate is 1.65Gbps/ch for inputting a UXGA pixel data signal with 2m cable.

关 键 词：DVI 时钟数据恢复 过采样 DPLL 

分 类 号：TN702[电子电信—电路与系统]