Bresenham直线光栅化算法的硬件实现方法研究  

Implementation of graphics accelerator of line raster based on Bresenham algorithm

作　　者：贾运宁[1] 赵峰[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《信息技术》2008年第9期132-134,137,共4页Information Technology

摘　　要：直线光栅化在图形绘制过程中占有很大比例,直线光栅化的速度也在很大程度上影响着显示芯片的加速性能。文中基于Bresenham算法,实现了单像素直线的光栅化。将二维平面八等分后,任意直线的光栅化根据对称性映射到一个固定区域进行,简化了硬件结构,提高了加速性能。基于FPGA平台(Xilinx的Virtex2pXC2VP30),该光栅化系统稳定运行在100MHz。Line raster occupies lots of proportions during the graphics drawing , and its speed influences the accelerating performance of the display chip. This paper based on Bresenham algorithm, implements the raster system of single-pixel line. According to symmetry, the discretional line＇s raster can be done by a simple procedure through partitioning the 2D plane into eight parts equally, which simplifies the architecture of hardware and improves the performance. The line raster system operates at 100MHz steadily based on FPGA platform （Xilinx＇ s Virtex2p _ XC2VP30）.

关 键 词：BRESENHAM FPGA 对称性 直线光栅化 

分 类 号：TP301.5[自动化与计算机技术—计算机系统结构]