SRAM的高成品率优化设计技术  

Technology of Design to Optimize SRAM for Higher Yield

作　　者：周清军[1] 刘红侠[1] 吴笑峰[1] 陈炽[1] 

机构地区：[1]西安电子科技大学宽禁带半导体材料与器件国家重点实验室,西安710071

出　　处：《固体电子学研究与进展》2008年第3期449-454,共6页Research & Progress of SSE

基　　金：国家自然科学基金资助(60206006);国防预研基金资助(51308040103);西安应用材料创新基金资助(XA-AM-200701)

摘　　要：提出了一种嵌入式SRAM的高成品率优化方法:通过增加冗余逻辑和电熔丝盒来代替SRAM中的错误单元。利用二项分布计算最大概率缺陷字数,从而求出最佳冗余逻辑。将优化的SR SRAM64 K×32应用到SoC中,并对SR SRAM64K×32的测试方法进行了讨论。该SoC经90 nm CMOS工艺成功流片,芯片面积为5.6 mm×5.6 mm,功耗为1997 mW。测试结果表明:优化的SR SRAM64 K×32在每个晶圆上的成品数增加了191个,其成品率提高了13.255%。In order to optimize embedded SRAM for higher yield, presented is a method of adding redundancy logic and E-FUSE box to replace the faulty units of SRAM in this paper. By means of binomial distribution to count the faulty words of max probability, the optimum redundant logic is calculated. The SR SRAM64K × 32 optimized is used in SoC and the testing method of the SR SRAM64K × 32 is discussed. The SoC design has been successfully implemented in a Chartered 90nm CMOS process. The SoC chip occupies 5.6 mm × 5.6 mm in die area and consumes 1997mW. The testing results indicate that the number of good SR SRAM64 K × 32 per wafer is increased by 191 and the yield gain is 13. 255%.

关 键 词：优化 自我修复静态随机存储器 冗余数据寄存器 成品率 

分 类 号：TN402[电子电信—微电子学与固体电子学]