面向人工神经网络算法的数字VLSI设计及实现  

Digital VLSI Design and Realization for Artificial Neural Network Algorithms

作　　者：钱艺[1] 王沁[1] 吴巍[1] 闫晓风[1] 

机构地区：[1]北京科技大学信息工程学院,北京100083

出　　处：《信息与控制》2008年第5期615-620,共6页Information and Control

摘　　要：设计了一种数据位长可变的基于MIMD(Multiple Instruction Multiple Data)结构的通用人工神经网络并行处理器APP(ANN’s Parallel Processor),具有8位、16位、32位等三种数据位模式.优化了处理器的关键运算部件和内部数据通路,并且定制了类RISC指令集,能够通过编程来实现多种ANN算法.APP处理器基于0.25μm的CMOS工艺设计,使用Cadence公司工具对其进行综合,并与其它的神经网络实现手段进行比较.实验结果表明,该处理器具有较好的通用性和实时性.A general artificial neural network parallel processor APP （ANN＇s Parallel Processor） with 8, 16, 32 bit data modes based on MIMD （Multiple Instruction Multiple Data） architecture is proposed, of which the data bit can be changeable. The key operation units and the inner data path are optimized, and the RISC-like instruction set is also customized with which several ANN algorithms can be realized. The APP processor is designed with the 0.25μm CMOS technology and is synthesized with tools from Cadence Inc. Experiement results show that comparing with other neural implementation ways, the proposed APP has a better performance in versatility and real-time ab.ility.

关 键 词：MIMD 神经网络 处理器 位长可变 

分 类 号：TP183[自动化与计算机技术—控制理论与控制工程]