用于流水线ADC的预运放-锁存比较器的分析与设计  

Analysis and Design of Pre-amplifier-Latch Comparator Fitting for Pipeline ADC

作　　者：吴笑峰[1] 刘红侠[1] 石立春[1] 周清军[1] 胡仕刚[1] 匡潜玮[1] 

机构地区：[1]西安电子科技大学微电子学院,宽禁带半导体材料与器件教育部重点实验室,陕西西安710071

出　　处：《湖南大学学报（自然科学版）》2008年第11期49-53,共5页Journal of Hunan University:Natural Sciences

基　　金：国家自然科学基金资助项目(60206006);国防预研基金资助项目(51308040103);西安应用材料创新基金资助项目(XA-AM-200701)

摘　　要：提出了一种应用于开关电容流水线模数转换器的CMOS预运放-锁存比较器.该比较器采用UMC混合/射频0.18μm 1P6M P衬底双阱CMOS工艺设计,工作电压为1.8 V.该比较器的灵敏度为0.215 mV,最大失调电压为12 mV,差分输入动态范围为1.8 V,分辨率为8位,在40 M的工作频率下,功耗仅为24.4μW.基于0.18μm工艺的仿真结果验证了比较器设计的有效性.A CMOS preamplifier-latch comparator used in switched-capacitor pipeline analog-to-digital converter was presented, The comparator was designed under UMC Mixed-Mode/RF 0.18μm 1P6M P-Sub Twin- Well CMOS process and worked with 1.8V power supply. The sensitivity of the comparator was 0. 215 mV, the largest offset voltage was 12 mV, the differential input range was 1.8 V, the resolution was 8 bit and the power dissipation was only 24.4 μW at 40 MHz. HSPICE simulations of the comparator implemented in a 0.18μm technology demonstrate its effectiveness.

关 键 词：预运放-锁存比较器 流水线ADC 踢回噪声 分析与设计 

分 类 号：TN432[电子电信—微电子学与固体电子学]