一种高速浮点加法器的优化设计  

Optimized design of fast floating-point adder

作　　者：冯为[1] 王波[1] 孙一[1] 金西[1] 

机构地区：[1]中国科学技术大学物理系微电子学教研室,合肥230026

出　　处：《电子测量技术》2008年第11期4-8,共5页Electronic Measurement Technology

摘　　要：高性能浮点加法器是现代微处理器中的重要部件,是实时图像处理和数字信号处理的核心,同时也是微处理器数据处理的关键路径,其完成一次加法操作的周期基本决定了微处理器的主频。本文介绍了一种高速浮点加法器的优化设计,它通过采用基于Two-Path算法的错位并行改进算法;在前导零预测电路设计中采用并行预测;尾数的54位CLA加法器中采用NAND门来代替以前CLA中常用的NOT门和AND门等一系列的改进措施,从而提高了浮点加法器的速度,使得加法运算由传统的5周期变成3周期,经仿真验证后,加法器的频率能达到350MHz。经仿真验证后,采用逻辑门比传统的浮点加法算法节省了23%。High-performance floating-point adder is the important parts of modern microprocessors, also is the real-time image processing and digital signal processing core, and the key to the microprocessor data-processing path, the cycle of basic addition operation decided the micro-frequency of the device. We present a new design of IEEE compliant double precision floating point adder by using various optimization techniques, such as two data path separation, three pipdine stages,fastest 54 b CLA adder, a new LZA logic for high-speed floating-point adder, which introduces a pair of fast parallel anticipatory arithmetic to anticipate leading-zero bits of the result of subtraction without knowing whether the reset is positive or negative. All of above effectively increase the speed of floating-point adder unit, After verification, the adder could achieve high performance up to 350MHz, and could save 23% logic gates compare to traditional algorithm.

关 键 词：浮点加法器 Two-Path算法 错位并行 NAND 前导零 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]