高压SOI器件介质场增强  

Dielectric Layer Field Enhancement for High Voltage SOI Devices

作　　者：李肇基[1] 张波[1] 罗小蓉[1] 胡盛东[1] 

机构地区：[1]电子科技大学、电子薄膜与集成器件国家重点实验室,四川成都610054

出　　处：《电力电子技术》2008年第12期36-38,56,共4页Power Electronics

摘　　要：提高纵向耐压是研究绝缘体上的硅(Silicon-on-insnlator,简称SOI)高压器件之瓶颈,经过多年研究,总结出了SOI高压器件介质场增强(Enhanced Dielectric Layer Field,简称ENDIF)理论与技术,通过增强介质埋层电场来提高击穿电压。给出增强介质埋层电场的3项技术,即在埋层上界面引入电荷、降低埋层介电系数、采用超薄顶层硅。基于ENDIF,提出了一系列SOI高压器件结构,即电荷型SOI高压器件、低k和变k埋层SOI高压器件、薄硅层阶梯漂移区SOI高压器件,建立了相应的耐压模型,并研制出大于700V的双面电荷槽SOI横向扩散金属氧化物半导体(Laterally Diffused Metal Oxide Semiconductor,简称LDMOS)。Vertical breakdown voltage improvement is the bottleneck of SOl high voltage.Our team has researched on this for many years, and summarized the theory and technology of enhanced dielectric layer field （ENDIF）,in which breakdown voltage is increased by enhancing dielectric layer electric field.Three approaches which can enhance dielectric layer electric field are given：implementing the interface charges between silicon and dielectric layer;introducing low permittivity （LK） dielectric into buried layer and enhancing the critical electric field in silicon at the interface of Si/dielectric layer by using a thin silicon layer.Based on ENDIF, a series of SOl high voltage device structures is proposed：SOI high voltage device structure with charge mode, SOl high voltage device structure with low k dielectric buried layer and thin Si layer SOl high voltage device structure with step drift region.Analytical models for the electric field and the breakdown voltage have been developed and the breakdown voltage larger than 700 V is obtained in SOl LDMOS with double-side trench on 20 μm SOl layer and 1 μm buried oxide layer.

关 键 词：电场 绝缘/介质场增强 高压器件 

分 类 号：TN386[电子电信—物理电子学]