组合电路内建自测试技术的研究  

Research on Built-in Self Test Technology of Combinational Circuit

作　　者：杨兴[1] 胡正伟[1] 

机构地区：[1]华北电力大学电子与通信工程系,河北保定071003

出　　处：《电子质量》2008年第12期3-7,共5页Electronics Quality

摘　　要：随着集成电路技术的发展,可测性设计在电路设计中占有越来越重要的地位,内建自测试作为可测性设计的一种重要方法也越来越受到关注。文中首先介绍了内建自测试的实现原理,在此基础上以八位行波进位加法器为例,详细介绍了组合电路内建自测试的设计过程。采用自顶向下的设计方法对整个内建自测试电路进行模块划分,用VHDL语言对各个模块进行代码编写并在QuartusII软件环境下通过了综合仿真,结果表明此设计合理,对电路的测试快速有效。With the development of integrated circuit technology, the design for test occupies an increasingly important position in circuit design, and the built-in self-test（BIST）, a mean of design for test technologies is also catches more and more attention. The BIST of the principle of achieving is introduced first in this paper, then take the 8-bit ripple carry adder as an example, describes the design process of BIST, Use the top-down approach to divide the whole circuit, carries out the programming with the VHDL to each module and through the comprehensive simulation under the Quartusll software. The results show that this design is rational, and makes the test of circuit go quickly and effectively.

关 键 词：内建自测试 可测性设计 行波进位加法器 组合电路 

分 类 号：TN407[电子电信—微电子学与固体电子学]