基于FPGA的快速中值滤波算法  

FPGA-based algorithm of fast median filter

作　　者：王宇新[1] 贺圆圆[1] 郭禾[1] 龙珠[1] 

机构地区：[1]大连理工大学计算机科学与技术系,辽宁大连116023

出　　处：《计算机应用研究》2009年第1期224-226,共3页Application Research of Computers

基　　金：国家自然科学基金资助项目(60675008)

摘　　要：针对传统中值滤波算法排序量多、速度慢的缺点,提出了一种基于FPGA的中值滤波快速算法。充分利用两个相邻滤波窗口中的相关排序信息,随着一列新像素的移入,同时更新已有的排序信息,从而完成中值滤波处理。该算法将每个窗口查找中值的比较次数降到很低,达到了快速抑制噪声及保持图像细节的目的。In order to solve the problem that the speed of classical median filter was slow because of a lot of sorting,this paper proposed a new algorithm of median filter based on FPGA. It made full use of the coherence of data adjacent windows and completed the median filter processing by adding the new column of pixels while updating the rest of the arranged pixels. The algorithm can reduce the number of comparisons, and achieve the goal of noise suppression and image details keeping in a fast speed.

关 键 词：现场可编程门阵列 中值滤波 VERILOG 实时图像处理 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]