4 Gbps低功耗并串转换CMOS集成电路  

4 Gbps Low Power Serializer CMOS IC

作　　者：卞振鹏[1] 姚若河[1] 郑学仁[1] 

机构地区：[1]华南理工大学微电子研究所,广州510640

出　　处：《电子与封装》2009年第2期21-23,40,共4页Electronics & Packaging

摘　　要：为满足传输数据的高速低功耗的要求,文章设计了一种半速率时钟驱动的二级多路选择开关式的10:1并串转换器。第一级为两个5:1的并行串化器,共用一个多相发生器。多相发生器由五个动态D触发器构成。第二级为一个2:1的并行串化器。采用半速率时钟、多路选择开关结构降低了大部分电路的工作频率,降低了工艺要求,也降低了功耗。通过调整时钟与数据间的相位关系,提高相位裕度,降低了数据抖动。采用1.8V0.18μm CMOS工艺进行设计。用Hspice仿真器在各种PVT情况下做了仿真,结果表明该转换器在输出4Gbps数据时平均功耗为395μW,抖动18s-1。A two-stage multiphase 10-bit serializer was designed in order to meet the demand of low-power and high-speed transmission. It is driven by half rate clock. The first stage is constructed by two 5：1 multiphase serializers, which share a multiphase clock generator. The multiphase clock generator is constructed by 5 dy- namic D Flip-Flops. The second stage is a 2：1 multiphase serializer. Using half rat clock and multiphase type decreases the speed of most modules, which makes process easier, and decreases the power consumption. The jitter is reduced by improving phase margin. The serializer is based on 1.8 V 0.18 μ m CMOS technology. It was simulated at all kinds of PVT conditions by Hspice. Results show that its power disSIPation is 395 μ W and its jitter is 18 s^-1 at 4 Gbps bit rate.

关 键 词：并串转换器 高速 低功耗 多相时钟发生器 CMOS 

分 类 号：TN43[电子电信—微电子学与固体电子学]