10.5GHz1:2静态分频器设计与实现  

Design and Realization of 10.5 GHz 1∶2 Static Frequency Divider

作　　者：张敏[1] 张有涛[1] 陈新宇[1] 

机构地区：[1]南京电子器件研究所,南京210016

出　　处：《固体电子学研究与进展》2008年第4期516-519,共4页Research & Progress of SSE

摘　　要：采用0.18μm CMOS工艺设计并实现了1∶2静态分频器。设计中为达到高速率和高灵敏度,对传统的SCFL结构D触发器进行了拓扑及版图优化。测试结果表明,电源电压为1.8V时,该分频器最高工作频率高于10.5GHz,最低工作频率低于2.5MHz(受测试条件限制),输入信号0dBm时的工作频率范围为2.5MHz～9.4GHz,芯片核心功耗9mW,核心面积50μm×53μm。An 1 ： 2 static frequency divider is realized in 0. 18 um standard CMOS technology. By optimizing the topology and layout of the traditional SCFL D-flip-flop, high speed and high sensitivity are achieved. Test results show that the maximum operation frequency is higher than 10. 5 GHz and the minimum operation frequency is lower than 2.5 MHz, under the existed equipment condition. And the operation frequency range at 0 dBm input signal is 2.5 MHz- 9.4 GHz. The core circuit consumes 9 mW from a 1.8 V supply and occupies 50 um×53 um.

关 键 词：分频器 触发器 互补金属氧化物半导体 集成电路 

分 类 号：TN401[电子电信—微电子学与固体电子学]