Cu通孔诱导的应力对CMOS迁移率影响分析  

Analysis of the Influence of Stress Induced by Cu Via on CMOS Mobility

作　　者：许建华[1] 汪辉[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《半导体技术》2009年第3期221-224,共4页Semiconductor Technology

基　　金：国家自然科学基金资助项目(NSFC60606015);上海市浦江人才计划资助项目(05PJ14068);上海交通大学微电子学院科研基金资助项目

摘　　要：利用Si片中填充Cu通孔技术实现芯片间互连是目前最有前景的三维芯片技术。利用有限元模型仿真研究了Cu通孔在Si中引起的诱导应力对CMOS晶体管迁移率的影响。分析了键合力、键合温度、通孔直径和Si片厚度等因素的影响。研究发现,Si中诱导应力的主因是键合温度,且诱导应力随Si片厚度降低而减小。同时,晶体管免受区正比于通孔的直径,且PMOS迁移率变化率对应力的敏感程度要大于NMOS,因而PMOS的免受区决定整个CMOS工艺的免受区。The most promising 3D chip technology currently is to attain the interconnection of dies by Cu via on Si. Finite element model was used to study the influence of the stress in Si induced by Cu via on the mobility of CMOS transistor. A number of factors including bonding force, bonding temperature, diameter of via and thickness of Si were studied. It is found in simulation that the bonding temperature is the main cause for the induced stress, and the induced stress decreases as the thickness of die decreases. Moreover, the immune zone of transistor is proportional to the diameter of Cu via, and the change of mobility in PMOS is more sensitive to the induced stress in Si than that in NMOS, therefore, the immune zone of PMOS determines that of CMOS process.

关 键 词：通孔 键合 应力 迁移率 芯片互连 3D芯片技术 

分 类 号：TN304.1[电子电信—物理电子学] TN305.9