1.5 V 0.35μm CMOS 3.2 Gb/s 1:4分接器设计  

Design of 1.5 V 3.2 Gb/s Demultiplexer in 0.35 μm CMOS Process

作　　者：邱玲[1] 冯军[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《上海交通大学学报》2007年第S2期24-27,共4页Journal of Shanghai Jiaotong University

摘　　要：采用CSM 0.35μm CMOS工艺,设计了低电压高速1∶4分接器.分接器采用半时钟树型结构,由1个高速1∶2分接器和2个低速1∶2分接器级联而成.整个电路实现的基本单元为共栅动态负载锁存器.电路最高可工作在3.2 Gb/s,电源电压为1.5 V,整体电路功耗约为120 mW,芯片面积为0.675 mm×0.675 mm.Using tree-type structure,a low voltage and high speed 1∶4 demultiplexer(DEMUX) based on CSM 0.35 μm CMOS process was presented.It is made of a high-speed 1∶2 DEMUX and two parallel low-speed DEMUX.This circuit employs the common-gate dynamic-loading latch as its basic cell.The simulation result shows the highest working rate can be up to 3.2 Gb/s on 1.5 V supply,with a total power consumption of about 120 mW.The chip size is 0.675 mm×0.675 mm.

关 键 词：分接器 低电压 CMOS 动态负载 

分 类 号：TN386[电子电信—物理电子学] TN253