抗干扰插值迟早门扩频跟踪构架  

Interpolation-based anti-jamming E-D-gate DS-SS code tracking architecture

作　　者：田宇[1] 李国通[1] 杨根庆[1] 

机构地区：[1]中国科学院微小卫星联合重点实验室,上海200050

出　　处：《中国科学院研究生院学报》2009年第4期513-516,共4页Journal of the Graduate School of the Chinese Academy of Sciences

摘　　要：为了降低接收机功耗,提出一种基于插值的单倍采样接收机架构.性能分析显示,在具备成形滤波器的情况下,此构架仅以不足0.1dB的损失为代价,将抗干扰计算量降低了一半,从而极大地降低了接收机计算负担和整体功耗.DS-SS is widely used in LEO satellite communication. Since jamming exists in UHF/VHF wave band, which is commonly selected by LEO communication system, anti-jamming module is necessary in receivers. To control the power consuming, an interpolation-based one-sample-per-chip receiver architecture is developed. Performance analyses show that this architecture cuts off half of anti-jamming module computation burden at the cost of the SNR lose less than 0. 1 dB. By this approach, computation burden and power consuming can be reduced remarkably.

关 键 词：插值 迟早门 抗干扰 低功耗 

分 类 号：TN91[电子电信—通信与信息系统]