基于FPGA的RS232异步串行口IP核设计  

Design of RS232 asynchronous serial port IP-core based on FPGA

作　　者：李金力[1] 刘文怡[1] 彭旭峰[1] 

机构地区：[1]中北大学电子测试技术国防科技重点实验室

出　　处：《电子设计工程》2009年第8期31-32,35,共3页Electronic Design Engineering

基　　金：国家973基金项目(2007CB316504)

摘　　要：为增加系统稳定性,减小电路板面积,提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言对接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性,可根据需要实现功能的升级、扩充和裁减。In order to enhance the stability of the system and reduce the board area, an asynchronous serial IP core design is proposed based on FPGA.VHDL hardware description language has been used for sending and receiving module design. The design has been simulated in the Xilinx ISE environment.Finally,the UART IP core is embedded in FPGA to realize the asynchronous serial communication function .This IP core is modularity, compatibility and configurable. According to the need of function, the system design can realize upgrade, expansion and cuts.

关 键 词：FPGA 异步串行口 VHDL IP核设计 

分 类 号：TP274.5[自动化与计算机技术—检测技术与自动化装置]