基于阵列除法的数据接收/显示模块设计  

Design of a radar altimeter data receiver and display module based on nonrestoring array divider

作　　者：林华[1] 刘建新[1] 

机构地区：[1]中国工程物理研究院电子工程研究所,四川绵阳621900

出　　处：《信息与电子工程》2009年第4期304-307,共4页information and electronic engineering

摘　　要：主要介绍基于FPGA的脉冲雷达高度表串行高度数据接收/显示模块的设计。在系统讨论异步串行高度数据接收/显示模块的内部结构的基础上,提出了以不恢复余数除法为基础的BIN码到BCD码的转换算法,并构造了以移位、加/减法为基础的阵列除法器。该算法速度快,逻辑简单,非常适合实时性要求较强的场合。最后通过仿真波形验证其内部时序的正确性。Based on FPGA implementation, the serial data receiver and display module for the pulse radar altimeter was designed. The inner structure of the asynchronous serial height data receiver and display module was discussed systematically. The algorithm of the binary（BIN） code converting to the Binary Coded Decimal（BCD） code based on nonrestoring array division was put forward. The array divider based on shift and Controllable Addition and Subtraction（CAS） was built. The algorithm was suitable to real time applications for its high calculation speed and simple logic. The timing of the receiver module was validated through the simulation.

关 键 词：雷达 BIN码 BCD码 VERILOG HDL语言 现场可编程门阵列 

分 类 号：TN957.5[电子电信—信号与信息处理]