采用容性封装技术提高ESD防护性能研究  

Study on Robustness Improved ESD Protection Method by Capacitive Packaging Technology

作　　者：曾传滨[1] 海潮和[1] 李晶[1] 李多力[1] 韩郑生[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2009年第9期876-880,共5页Semiconductor Technology

摘　　要：提出了一种通过在电源线与地线之间加入外部电容以吸收ESD脉冲的新型集成电路ESD保护方法。分析了这种方法在提高产品ESD防护性能方面的可行性,并用TLP设备测量出了一0.1μF电容在吸收4A TLP ESD电流脉冲时电容两端电压随时间的变化曲线以及不同电容值电容吸收4A TLP ESD电流脉冲后的电压随电容变化曲线,理论分析及测试结果均表明这种ESD防护方法能在集成电路承受6000V HBM ESD脉冲时将VDD与GND之间的电压降钳位在0.5V以下。通过将此ESD防护方法应用在SOI微处理器产品和SOI静态随机存储器产品上,成功地将这两款产品的ESD防护能力从1000V提高到了3000V以上,验证了这种容性封装技术在ESD防护方面的优良性能。A new IC electrostatic discharge （ESD） protection method was proposed by packaging an exterior capacitor between VDD and GND to absorb ESD pulse. The possibility of improving the IC ESD robustness was analyzed. The voltage-time curve for 0.1 μF capacitor and capacitance-voltage curve for different capacitors were measured by transmission line pulse （TLP） system when the capacitors absorb 4 A TLP ESD current pulse. Both the analysis and experiment results indicate that the ESD protection method can get less than 0.5 V voltage drop between EBB and Vss power wires during 6 000 V HBM ESD pulse. By applying this ESD protection method in an SOI microprocessor and an SOI static random access memory （SRAM） product, the chips ESD robustness is successfully improved from beneath 1 000 V to above 3 000 V, which demonstrates that this capacitive packaging technology can well improve the IC ESD robustness.

关 键 词：静电放电 电容 封装 传输线脉冲发生器 钳位电路 集成电路 

分 类 号：TN305.94[电子电信—物理电子学]