基于片上PLL时钟的at-speed测试设计  

At-Speed Testing Scheme for a Design with Internal PLL

作　　者：孙大成[1] 

机构地区：[1]中国电子科技集团公司第三十八研究所,合肥230031

出　　处：《中国集成电路》2009年第10期34-37,47,共5页China lntegrated Circuit

摘　　要：深亚微米制造工艺的广泛采用及越来越高的芯片工作频率,使得具有时序相关的芯片缺陷数量不断增加,at-speed测试成为对高性能电路进行测试的必要技术。文章首先介绍了at-speed测试的故障模型,以及具体测试方法,然后详细介绍了采用PLL时钟作为at-speed测试时钟时,一款芯片的at-speed测试实现方案,最后采用Fastscan及TestKompress对整个设计进行了测试向量自动生成及向量压缩。实验结果表明此方案可行,采用TestKompress进行设计更符合目前的设计需求。Widely-used deep submicron processes and higher chip frequency, which result in increasing timing-related defects, make at-speed testing the necessary techniques for testing high performance circuits. Firstly, at-speed testing fault models and methods are introduced, then this paper presents the at-speed testing scheme on a real design with internal PLL. At last ATPG and pattern compression are made by using Fastscan and TestKompress The results indicate this scheme is feasible, and TestKompress is suitable to meet the recent design requirements.

关 键 词：At—speed测试 可测性设计 自动测试向量生成 

分 类 号：TN407[电子电信—微电子学与固体电子学]