门控时钟单元IP核设计  

Clock Gating Cell IP Core Design

作　　者：陈志强[1] 潘兰芳[1] 韩安太[1] 吴秀山[1] 

机构地区：[1]中国计量学院电路与电子技术研究所,浙江杭州310018

出　　处：《中国集成电路》2009年第10期43-47,共5页China lntegrated Circuit

基　　金：国家自然科学基金资助项目(批准号:90207001)

摘　　要：门控时钟是VLSI设计中降低功耗的一种主要技术,将门控时钟设计为一个独立的IP,可以降低设计的复杂性。在对门控时钟的基本工作原理和结构分析的基础上,本文给出了将门控时钟单元电路设计为一个独立IP核的设计流程,并生成了系统物理设计和验证阶段所需要的库文件。设计结果已成功地应用于高性能、低功耗嵌入式CPU的设计。Gated Clock is a major approach to reduce power consumption in VLSI design. Clock-gating as an independent IP core, may reduce the complexity of the design. Based on analyzing the operation structure, a detail flow for clock-gating IP core design was presented, the library files attached to the IP generated for physical lower power embedded design and verification. The designed IP core has been used to design a high CPU successfully. cell designed principle and core was also performance,

关 键 词：门控时钟单元 IP核 低功耗 静态时序分析 

分 类 号：TN47[电子电信—微电子学与固体电子学]