深亚微米工艺ESD电路设计参数研究  

Study of Parameters Limiting ESD Performance in Deep Submicron process

作　　者：李志国[1] 岳素格[1] 孙永姝[1] 

机构地区：[1]北京微电子技术研究所,北京100076

出　　处：《微电子学与计算机》2009年第11期90-94,共5页Microelectronics & Computer

摘　　要：通过器件级仿真来评估ESD保护器件的鲁棒性的方法,对ESD电路的关键设计参数进行了研究.通过器件仿真软件MEDICI对栅极到源极接触孔的距离,栅极到漏极接触孔的距离以及栅极的宽度和长度对ESD性能的影响进行了研究,并分析了它们的失效机理.从而得出经验公式,可以在流片前估算出器件的ESD失效电压.通过在设计阶段预测器件的ESD性能可以缩短设计周期,节约成本.In this paper, a novel approach that performs device levd simulation to evaluate the robustness of the ESD protection device is presented. Several key parameters, such as the spacing from gate to source contact, the spacing from gate to drain contact, the length of the gate and the width of the gate are researched using the simulator MEDICI. The failure mechanism was also studied. An empirical equation is derived based on the simulation to calculate the failure threshold of the device. The prediction of ESD protection circuit performance in early design phase shortens the design cycle and reduces the cost.

关 键 词：ESD NMOS 击穿 仿真 

分 类 号：TN406[电子电信—微电子学与固体电子学]