Garfield系列SoC芯片可测性设计与测试  

Design-for-Testability and Test of Garfield Series SoC’s

作　　者：蔡志匡[1] 黄凯[1] 黄丹丹[1] 时龙兴[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,南京210096

出　　处：《微电子学》2009年第5期593-596,共4页Microelectronics

基　　金：国家自然科学基金资助项目"基于测试压缩和LBIST的系统芯片低成本测试技术研究"(90407009)

摘　　要：随着生产工艺的进步和芯片复杂度的增加,SoC芯片的测试问题显得越来越重要,传统的测试方法已不能满足现在的设计要求。文章介绍了基于130nm工艺的Garfield芯片可测性设计,包括边界扫描测试、存储器内建自测试、全速扫描测试和参数测试;分析了全速测试时钟的生成和测试压缩电路的实现。实验结果表明,该方案的故障覆盖率和压缩效率最高可达到97.39%和30%,符合工程应用要求。With the development of process technology and increasing complexity of IC＇s, SoC test is becoming a challenge. Conventional test methods no longer fit the current design. P, ased on SMIC＇s 130 nm CMOS technology, a design-for-testability （DFT） scheme for Garfield SoC＇s was presented, including boundary scan test, memory selfbuilt-in test, at-speed scan test and parameter test. Generation of full-speed test clock and implementation of compression circuit were analyzed as well. Test results showed that the novel design had a fault coverage of 97. 39% and maximum compression ratio of 30%, which met the requirement of engineering applications.

关 键 词：可测性设计 扫描 内建自测试 SOC 测试压缩 全速测试 

分 类 号：TN407[电子电信—微电子学与固体电子学]