雷达数字脉压在FPGA上的研究与实现  

Research and Realization of Radar Digital Pulse Compression Based on the FPGA Chips

作　　者：张学辉[1] 邱军海 

机构地区：[1]中国石油大学(华东)计算机与通信工程学院,山东东营257061 [2]烟台工程职业技术学院机电工程系,山东烟台264006

出　　处：《计算机工程与科学》2009年第11期142-144,共3页Computer Engineering & Science

摘　　要：采用FPGA技术实现雷达数字脉压,克服了DSP处理速度有限、实时性差的问题。本文以自行研制的雷达信号处理PCI卡为平台,详细介绍了数字脉压在FPGA芯片上实现的原理和过程,对脉压中的匹配滤波器进行了优化设计,解决了FP-GA资源相对有限的问题。最后说明了利用FPGA进行数字脉压的优势,为雷达数字脉压的工程实现提出了一条新思路。FPGA is used to realize radar digital pulse compression, which overcomes the problems of limited processing speed and poor real-time performance of DSP. Based on the PCI radar signal processing platform developed by ourselves, the principle and process of realizing digital pulse compression based on FPGA is introduced, in which an optimal design on the filter for digital pulses is studied to solve the problem of the limited resources in FPGA. The advantages of using FPGA in digital pulse compressionare are shown by the simulation results , which supplies a new method for the implementation of radar digital pulse compression.

关 键 词：雷达 数字脉冲压缩 FPGA 

分 类 号：TN957[电子电信—信号与信息处理]