提高功率多芯片模块终测成品率的方法探讨  

Discussion on How to Improve Final Test Yield of Power MCM

作　　者：邵一琼[1] 汪辉[1] 任炜星[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《半导体技术》2009年第11期1078-1081,共4页Semiconductor Technology

摘　　要：根据功率多芯片组装模块成品率低的现状,分析比较了芯片级成本和模块总成本随模块中芯片数量和模块成品率而变化的关系,提出了临界成品率的概念。建立了典型的成本模型,得出了临界成品率随芯片数量的变化趋势,并给出了单芯片、双芯片到4芯片的成本曲线和临界成品率,分别为89%,94%和98%。对于由某一封装原材料引起的模块低成品率,也存在临界成品率,建立了典型公式,阐明了如何计算这一临界成品率。针对功率多芯片模块的成品率问题主要集中在功率芯片的UIS和Rdson参数上,给出加强这两个参数的测试能力和准确性的方法建议。According to the low-yield status of power muhi-chip module （MCM） assembly, the relation between the chip-scale cost and the total modules cost changing with the number of chips in the module and the module yield were analyzed and compared, critical yield concept was proposed. A typical cost model was established and the changing trend of critical yield with the number of chips was obtained, cost curve and the critical yield of single-chip, two chips up to four chips of 89%, 94% and 98% were given, respectively. As for the low yield caused by a certain packaging raw material, the issue of critical yield also exists. A typical formula was established for calculating the critical yield. Since the yield issues of MCM mainly focuses on parameters of power chips UIS （unclamped inductive switching） and Rd a suggestion was proposed to strengthen the test capacity and the accuracy of the two parameters.

关 键 词：功率多芯片模块 晶圆测试 晶圆重测 终测 临界成品率 

分 类 号：TN307[电子电信—物理电子学]