一种AMR语音编码器的VLSI设计及FPGA实现  

VLSI Design and FPGA Implementation of AMR Speech Encoder

作　　者：郑海东[1] 王明江[1] 王进祥[1] 崔浩林[1] 商迪[1] 

机构地区：[1]哈尔滨工业大学微电子中心,黑龙江哈尔滨150001

出　　处：《微电子学与计算机》2010年第2期17-21,25,共6页Microelectronics & Computer

摘　　要：AMR(自适应多速率)语音编码标准由于其低码率和高质量,在通信和多媒体领域得到广泛应用.针对AMR语音编码标准的算法特点,提出了一种"音频DSP软核+硬件加速器"的VLSI实现结构.这种结构能够有效地实现编码算法,同时达到低成本、低功耗的要求.综合后的电路在满足语音编码实时性的要求下能工作在50MHz频率以下,功耗仅有不到50mW,和78k门的芯片面积.最后通过FPGA整体验证,证明这种方案是可行有效的.同时优化后的音频DSP软核和硬件加速器中的模块复用设计,使得本设计方案对G.7xx系列编码算法具有通用和可移植性.AMR（Adaptive Multi Rate）speech encoder have application in communication and multi media field widely for lower rate and higher quality. This paper presents a VLSI structure of ＂Audio DSP soft core ＋ Hardware accelerator＂ based on AMR speech coding algorithm. This structure can complete encoder algorithm with meeting the demand of low east and low power. The circuit can work steadily at 50MHz, and only have 50mW power and 78k chip area. This design was implemented on FPGA device, and the experimental results indicate that the structure is feasible. Meanwhile , as the design in this structure can also be applied in many other speech coding algorithms like G. 7XX serial.

关 键 词：AMR VLSI DSP软核 硬件加速器 FPGA 

分 类 号：TN4[电子电信—微电子学与固体电子学]