基于VerilogHDL的MTM总线从模块有限状态机设计  

Design of MTM Bus Slave Module's Finite State Machine Based on Verilog HDL

作　　者：陈星[1] 黄考利 连光耀 王振生 

机构地区：[1]军械工程学院,河北石家庄050003 [2]军械技术研究所,河北石家庄050003

出　　处：《仪表技术》2010年第2期25-27,30,共4页Instrumentation Technology

摘　　要：针对MTM总线从模块的设计需求,在分析MTM总线通信协议基础上,给出了MTM总线从控制模块的有限状态机模型。该有限状态机作为从控制模块的核心,主要用于完成控制MTM总线从模块的消息传送顺序。分析了MTM总线结构体系和有限状态机设计的主要方法步骤,通过QUARTUS II开发平台,基于Verilog HDL语言对该有限状态机进行了设计实现与仿真验证。基于该有限状态机的MTM总线从通信模块已经设计实现,并在工程中得到应用,性能稳定。According to the demand of designing MTM slave module, on the base of analyzing the protocol of MTM bus, the model of MTM bus slave module＇s finite state machine is put forward in this paper. The FSM is the core of the slave module. It controls the transmission of the messages of the slave module. The structure of MTM bus and the mainly methods of designing a FSM are introduced. A MTM bus slave module＇s finite state machine based on Verilog HDL is designed. The design is proved in the circumstance of QuartusII. The MTM slave module based on this FSM has been already realized and applied to the project, and the function is favorable.

关 键 词：VERILOG HDL 有限状态机 MTM总线 

分 类 号：TP206[自动化与计算机技术—检测技术与自动化装置]